The Design and Verification Conference (DVCon) has gained it’s popularity in its niche as one of the top conferences for the application of languages, tools, and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon US brings chip architects, systems designers, software developers, and IP integrators the latest methodologies, techniques, applications, and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.
Caused by Covid-19 all the conferences have been switched to online mode for over a year, and DVCon US’21 is not an exception. This year’s conference is to held virtually and as a participant, Optima is conducting a workshop.
Workshop: Achieving ISO 26262 ASIL Metrics Using Modern Static And Dynamic Failure Mode Fault Analysis
Automotive Functional Safety Analysis under the ISO 26262 standard has evolved over the last few years, as the challenges have become better-understood and respective solutions refined. Early approaches to demonstrate that devices meet specific Automotive Safety Integrity Level (ASIL) requirements have given way to more effective techniques and technologies. In this workshop, we present new solutions that accelerate and increase the accuracy of this development phase. To achieve an appropriate ASIL rating, an automotive semiconductor chip has to meet specific requirements prescribed in the standard. The Single Point Fault Metric (SPFM), Latent Point Failure Metric (LPFM) and the Failure in Time (FiT) metric are all critical measures that must be satisfied to a certain proportion. Different failure modes and safety mechanisms, analyzing varied permanent and transient fault types, and overall product requirements and time-to-market all factor into this analysis process.
Optima’s Functional Safety Solutions:
The Optima Safety Platform includes a set of solutions, or “apps”, built on top of the company’s FIE technology that automates key ISO 26262 verification requirements. The platform targets Hard and Soft Error analysis, essential in certifying the safe operation of automotive semiconductor devices to the ISO 26262 Functional Safety standard.
- Optima-SA™: Static analysis is an automated tool that provides early identification of Functional Safety implementation flaws and provides fault-mode sizing for the FMEDA process, debug of Functional Safety problems and others.
- Optima-HE™: Hard-error analysis is accelerated over 1,000X than existing solutions to measure diagnostic coverage, then automatically improve it using Optima’s Coverage Maximizer™ technology.
- Optima-SE™: Soft-error analysis may now be completed in a reasonable time, allowing reducing the FIT rate from transient-faults to close to zero with minimal silicon cost.
DVCon US exhibition is open on March 1-4.
Virtual conference, San Jose, US.
Anastasiya Sasnakevich is a digital marketing specialist with over 5 years’ of international experience. Having worked in different fields, Anastasiya found herself in automotive semiconductor industry where she has been working for almost 2 years. She holds Master Degree in International Business and Economics from BFSU, Beijing, and an MBA in Digital Marketing and Business from EFAP, Paris.